Package Design Engineer

At SPD Technology, we bring together a team of like-minded people who are driven by the desire to bring value through their work, united in their commitment to high performance and delivering custom, cutting-edge tech solutions that drive clients’ growth. We empower our people with a culture of excellence and enable them with the opportunity to uphold their accountability to contribute on each level. We value humanity and collaboration, encourage professional and personal growth, and foster a supportive and flexible work environment where everyone’s contribution is welcomed.

And now we are looking for a Package Design Engineer to join us as part of our team.

Be part of a team pushing the boundaries of semiconductor innovation by developing custom silicon solutions that power next-generation consumer and infrastructure products. You will contribute to technologies used at massive global scale, helping shape future hardware platforms with a strong focus on performance, efficiency, reliability, and system-level integration.

As a Chip Package Designer within the Silicon Integration team, you will develop package substrate designs for advanced 2.5D/3.5D packaging technologies used in high-performance ML and AI chips.

You will collaborate closely with Signal Integrity/Power Integrity (SI/PI), Thermal/Mechanical, Assembly, and PCB engineering teams to develop complex, high-performance substrate designs. The primary objective will be to optimize package substrate architecture for electrical performance, reliability, manufacturability, and assembly.

You will manage all major phases of the package design process, including routing feasibility studies, test vehicle development, product-level designs, design reviews, artwork export, DFM activities, and preparation of final manufacturing documentation.

You will also contribute to the evaluation and adoption of advanced chip packaging technologies within the broader silicon product development pipeline. Your work will directly support successful deployment of advanced computing systems in large-scale data center environments, helping optimize PPA (Power, Performance, Area) while improving overall system performance, power efficiency, and TCO (Total Cost of Ownership).

The broader AI and Infrastructure organization is focused on building next-generation computing platforms and infrastructure at exceptional scale, efficiency, reliability, and speed. These technologies support internal engineering teams, enterprise customers, and large-scale consumer-facing services worldwide.

The organization works across both hardware and software, including custom AI accelerators, advanced silicon platforms, AI infrastructure, large-scale networking, data center technologies, distributed computing systems, and systems research.

Fully remote role. Flexible schedule with participation in team ceremonies and cross-functional collaboration.

• Develop physical package substrate design of large form-factor package for ML high-performance computers (HPCs).
• Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity.
• Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
• Collaborate closely with signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
• Define and document the requirements for the package substrate design and bill of materials (BOM).

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
• 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
• Experience in chip package substrate layout, design verification, DFM and taping out for production.
• Experience in design automation and scripting.
• English — Upper Intermediate or higher.

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience in working with cross-functional teams including chip design, SI/PI, and PCB design teams.
• Experience in 2.5D/3.5D advanced package design.
• Experience in physical verification flow (LVS, DRC, connectivity).
• Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD).
• Ability to write scripts to customize elements of the Cadence or Mentor workflow.

Join the team of experts who create custom, cutting-edge tech solutions for world-renowned businesses, fueling clients growth. Unleash your potential, tackle new challenges, and be part of a team that values your skills and contributions. Focus on long-term impact and building tailored, long-lasting partnerships with our clients.

Work fully remote around the globe, or in a hybrid work model from our office hubs which are equipped with everything needed for comfortable work. Enjoy a flexible working schedule and create work and rest balance for yourself. Empower yourself with a stable workload and a stable income, focusing on lasting cooperation and high-performance culture.

Take advantage of performance review and career path. Elevate your skills with mentorship program, personal development plan, and individual learnings through the corporate library, public speaking support, and more.

Be among like-minded people and feel supported with collaboration, open communication and mutual respect. Join company-wide tech and cultural events, and contribute to meaningful CSR initiatives that resonate with your values.

Originally posted on Himalayas